
Chaitanya Kommu
Assistant Professor, Electrical Electronics and Communication Engineering, GST , VSP
Education
Ph. D.Email ID
Education
Ph. D.Education
Degree Name | Institute & College name | Year of Graduation/Award |
---|---|---|
Doctor of philosophy | Instrumentation Technology | 2022 |
Master of Technology | NIT ALLAHABAD | 2009 |
Bachelor of Engineering | GITAM COLLEGE OF ENGINEERING | 2006 |
Experience
Designation | Organization | From Date | To Date |
---|---|---|---|
ASSISTANT PROFESSOR | MVGR COLLEGE OF ENGINEERING | 10-06-2009 | 21-06-2010 |
TheDesignOfHighPerformanceThreeInputXorGateBasedOnCompoundGateMethodologyInternational Journal of Scientific & Technology Research , Scopus, MAR-Select, 9, 5376-5380
The Design of LowPower HighSpeed TwoLevel Three input XOR gateInternational Journal of Innovative Technology and Exploring Engineering (IJITEE), Google scholar, MAR-2020, 9, 1813-1818
The Mixed logic style based low power combinational circuits for ASIC design at 32nm Technology.CEJ JOURNAL, Google scholar, OCT-2019, VOLUME 10, 388-397
The Design of Static CMOS Memory Element using MixedLogic Style at 32nm TechnologyJournal of Information and Computational Science, Google scholar, SEP-2019, 9, 17-27
Design and Implementation of HighSpeed Low Power Compressors as standard cells for ASICsJETIR, Google scholar, -2019, 6, 17-24
The Mixed Logic Style based Low Power 2x1multiplexer for SOI designs at 32nm Technology IJRAR, Google scholar, -2019, Volume 6, 575-580
The Mixed Logic Style based Low Power and HighSpeed Onebit Binary adder for SOI Designs AT 32NM TechnologyInternational Journal of Recent Technology and Engineering, Scopus, NOV-2019, 8, 361-366
The Mixed Logic Style based Low Power andHigh Speed 32 Compressor for ASIC designs at32nm TechnologyInternational Journal of Engineering and Advanced Technology (IJEAT), Scopus, OCT-2019, 9, 43-49
A Novel Approach for High speed and Low power 4 bit Multiplier IOSR, EBSCO Host, -2012, 1, 1-4
FTL based Carry Look Ahead Adder Design using Floating GatesIJCA, EBSCO Host, -2011, 17, 1-5
Title of the book | Book / Chapter | Name of the publisher | Subject area | Edition | Page numbers | ISBN | Published year |
---|---|---|---|---|---|---|---|
Lecture Notes in Electrical Engineering | Chapters | Springer, Singapore | Micro Electronics | volume 434 | 191-200 | 18761119 | 2018 |
ERCICA | Chapters | Springer, New Delhi | Computing | Volume 1 | 41-52 | 978813222550 | 2015 |
Seminar name | Organized by | Venue | Start date | End date | Title of the paper presented | Role | Co presenter |
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Seminar name | Organized by | Venue | Start date | End date | Title of the paper presented | Role | Co presenter |
---|---|---|---|---|---|---|---|
International | IEEE FRANCIS XAVIER | TAMILNADU | 13-Dec-2018 | 14-Dec-2018 | HIGH PERFORMANCE 3 2 COMPRESSOR FOR HIGH SPEED ARCHITECTURES MULTIPLIERS | Participated | |
International | SPRINGER ASIC SERIES | VIETNAM | 29-Nov-2018 | 30-Nov-2018 | Implementation of Array Logic Functions using Mixed Logic Design Methodology for Low Power High Speed applications | Participated | |
International | SPRINGER | RAGHU ENGINEERING COLLEGE VIZAG | 06-Jun-2017 | 07-Jun-2017 | MODIFIED LOW POWER HYBRID 1BIT FULLADDER | Participated | |
International | SPRINGER | BANGALORE | 31-Jul-2015 | 01-Aug-2015 | NOVEL ASYNCHRONOUS ADDITION ARCHITECTURE FOR PORTABLE APPLICATIONS | Participated | |
International | ELSEVIER | BANGALORE | 01-Aug-2014 | 02-Aug-2014 | DESIGN AND IMPLEMENTATION OF HIGH SPEED AND LOW POWER COUNTER | Participated | |
International | IACSIT | Singapore | 01-Jun-2011 | 02-Jun-2011 | FTL Based Carry Look ahead Adder Design Using Floating Gates | Participated | |
International | VIT VELLORE | VIT VELLORE | 08-Oct-2009 | 09-Oct-2009 | A NOVEL HIGH SPEED MULTIPLEXER BASED FULL ADDER | Participated | Dr. Amit Dhavan |
International | VIT VELLORE | VIT VELLORE | 08-Oct-2009 | 09-Oct-2009 | A NOVEL HIGH SPEED MULTIPLEXER BASED FULL ADDER | Participated |
Title | Type | Organized by | Venue | Start date | End date | Role |
---|---|---|---|---|---|---|
Research Topics in VLSI and Industry Trends | Faculty development program | GMRIT | rajam | 29-May-2020 | 31-May-2020 | Participated |
SMART SYSTEMS | Quality improvement program | ANDHRA UNIVERSITY | ANDHRA UNIVERSITY | 21-Mar-2019 | 23-Mar-2019 | Participated |
MEMS DESIGN AND INTELLSUITE | Quality improvement program | GITAM GIT EIE | GITAM UNIVERSITY | 09-Nov-2018 | 10-Nov-2018 | Participated |
VLSI AND FPGA SIGNAL PROCESSING | Faculty development program | NIT WARANGAL | GITAM UNIVERSITY | 02-May-2018 | 07-May-2018 | Participated |
ANALOG AND DIGITAL COMMUNICATIONS | Faculty development program | GIT HYD | GITAM UNIVERSITY | 15-May-2017 | 24-May-2017 | Participated |
DSP AND APPLICATIONS | Faculty development program | NIT WARANGAL | GITAM UNIVERSITY | 09-Nov-2016 | 18-Nov-2016 | Participated |
ADVANCED COMMUTING USING MATLAB | Quality improvement program | GITAM GIT | GITAM | 25-Feb-2015 | 27-Feb-2015 | Participated |
OPTICAL FIBER COMMUNICATIONS AND PHOTONICS | Quality improvement program | GITAM | GITAM UNIVERSITY | 22-Feb-2014 | 22-Feb-2014 | Participated |
Title | Type | Organized by | Venue | Start date | End date | Role |
---|---|---|---|---|---|---|
Design, Implementation and Verification in VLSI | Quality improvement program | CoreEL | Online | 27-Apr-2020 | 01-May-2020 | Participated |
NPTEL | Faculty development program | IIT ROORKEE | VISAKHAPATNAM | 01-Feb-2019 | 20-Apr-2019 | Participated |
Nanofabrication Technologies | Faculty development program | IISc Bangalore | IISc Bangalore | 10-Sep-2018 | 12-Sep-2018 | Participated |
NANO SENSOR DESIGN PRINCIPLES AND APPLICATIONS | Quality improvement program | IIT HYDERABAD | IIT HYDERABAD | 03-Dec-2016 | 07-Dec-2016 | Participated |
MODELING SIMULATION AND CHARACTERIZATION OF NANO TRANSISTORS | Faculty development program | ELECTRICAL DEPARTMENT IIT KANPUR | IIT KANPUR | 26-Oct-2015 | 30-Oct-2015 | Participated |
APPLICATIONS OF NANO TECHNOLOGY | Quality improvement program | GIT AND UNIVERSITY OF TEXAS | GITAM UNIVERSITY | 06-Aug-2014 | 13-Aug-2014 | Participated |
LOW POWER PHYSICAL DESIGN AND SIGNOFF | Quality improvement program | IEEE PRIME ASIA | GITAM UNIVERSITY | 19-Dec-2013 | 19-Dec-2013 | Participated |
MISSION 10X Dale Carnegie Training | Quality improvement program | WIPRO | MVGR COLLEGE VIZAYANAGARAM | 07-Jun-2010 | 08-Jun-2010 | Participated |