Verilog Hardware Defination Language
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| 1.1 Hierarchy Scopes |
| 1.2 Concurrency |
| 1.3 Reserved Keywords |
| 1.4 Module Port Declerations |
| 1.5 Data Type Declarations |
| 1.6 Module Instances |
| 1.7 Primitive Instances |
| 1.8 Operators |
| 1.9 Contineous Assignment |
| 1.10 User Defined Primitives |
| 1.11 Synthesis Supported Constructs |
| 1.12 Systems Tasks and Functions |
| 1.13 Compiler Directives |