Syntax
gate_type (drive_strength)#(delay)instance_name[instance_array_range](terminal,terminal,...);switch_type #(delay)instance_name[instance_array_range](terminal,terminal,...);
Terminal Order
and
or
xornandxnor
nor(1_output, 1-or-more_inputs) bufnot(1-or-more_outputs, 1_input) bufif0
bufif1notif0
notif1(1_output, 1_input, 1_control) pulluppulldown(1_output) user-defined-primitives (1_output, 1-or-more_inputs)
Terminal Order
pmos
nmosrpmos
rnmos(1_output, 1_input, 1_control) cmosrcmos(1_output, 1_input, n_control, p_control) tranrtran(2_bidirectional-inouts) tranif0
rtranif0rtranif0
rtranif1(2_bidirectional-inouts, 1_control)
#delay or#(delay)
Single delay for all output transitions#(delay,delay)
Separate delays for (rising, falling) transitions#(delay,delay,delay)
Separate delays for (rising, falling, turn-off) transitions#(min_delay:typ_delay:max_delay)
Minimum to maximum range of delays for all transitions#(min_delay:typ_delay:max_delay,min_delay:typ_delay:max_delay)
Min. to max. range of delays for (rising, falling) transitions#(min_delay:typ_delay:max_delay,min_delay:typ_delay:max_delay,min_delay:typ_delay:max_delay)
Min. to max. range of delays for (rising, falling, turn-off) transitionsdelay (optional) represents the propagation delay through a primitive. The default delay is zero. Integers or real numbers may be used.
strength (optional) is specified as
(strength1,strength0)or(strength0,strength1)Refer to Logic Strengths for strength keywords.
Only gate primitives may have drive strength specified. Switch primitives pass the input strength to the output. Resistive switches reduce the strength as it passes through.instance_name (optional) may used to reference specific primitives in debugging tools, schematics, etc.
instance_array_range (optional) instantiates multiple primitives, each instance connected to separate bits of a vector.
The range is specified as[lhi:rhi](left-hand-index to right-hand-index). The primitive instances are connected with the right-most instance index connected to the right-most bit of each vector, and progressing towards the left. Vector signals must be the same size as the array. Scalar signals are connected to all instances in the array.
Primitive Instance Examples
Notes
and i1 (out,in1,in2);zero delay gate primitive and #5 (o,i1,i2,i3,i4);same delay for all transitions not #(2,3) u7(out,in);separate rise & fall delays buf (pull0,strong1)(y,a);output drive strengths model ECL wire [31:0] y, a;
buf #2.7 i[31:0] (y,a);array of 32 buffers