Logic Strengths

The Verilog HDL has 8 logic strengths: 4 driving, 3 capacitive, and high impedance (no strength). Strength Level Strength Name Specification Keyword Display Mnemonic 7 Supply Drive supply0 supply1 Su0 Su1 6 Strong Drive strong0 strong1 St0 St1 5 Pull Drive pull0 pull1 Pu0 Pu1 4 Large Capacitive large La0 La1 3 Weak Drive weak0 weak1 We0 We1 2 Med. Capacitive medium Me0 Me1 1 Small Capacitive small Sm0 Sm1 0 High Impedance highz0 highz1 HiZ0 HiZ1

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Literal Integer Number

Syntax size'base value Sized integer in a specific radix (base) size (optional) is the number of bits in the number. Unsized integers default to at least 32-bits. 'base (optional) represents the radix. The default base is decimal. Base Symbol Legal Values binary b or B 0, 1, x, X, z, Z, ?, _ octal o or O 0-7, x, X, z, Z, ?, _ decimal d or D 0-9, _ hexadecimal h or H 0-9, a-f, A-F, x, X, z, Z, ?, _ The ? is another way of representing the Z logic value. An _ (underscore) is ignored (used to enhance readability). Values are expanded from right to left (lsb to msb). When size is less than value, the upper bits are truncated. When size is larger than value, and the left-most bit of value is 0 or 1, zeros are left-extended to fill the size. When size is larger than value, and the left-most bit of value is Z or X, the Z or X is left-extended to fill the size. Examples Size Base Binary Equivalent 10 unsized decimal 0...01010 (32-bits) 'o7 unsized octal 0...00111 (32-bits) 1'b1 1 bit binary 1 8'Hc5 8 bits hex 11000101 6'hF0 6 bits hex 110000 (truncated) 6'hF 6 bits hex 001111 (zero filled) 6'hZ 6 bits hex ZZZZZZ (Z filled)

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Literal Real Number