Verilog HDL constructs that represent hierarchy scope are:
Each scope has its own name space. An identifier name defined within a scope is unique to that scope. References to an identifier name will search first in the local scope, and then search upward through the scope hierarchy up to a module boundary.
Introduction
Register
Data Types
New Data
Types
Other Data
Types
Data Type Declaration
Examples
Introduction
Syntax
register_type [size]variable_name,variable_name,...;register_type [size]memory_name[array_size];net_type [size] #(delay)net_name,net_name,...;net_type (drive_strength) [size] #(delay)net_name=continuous_assignment;trireg (capacitance_strength) [size] #(delay,decay_time)net_name,net_name,...;parameterconstant_name=value,constant_name=value,...;specparamconstant_name=value,constant_name=value,...;eventevent_name,event_name,...;delay (optional) may only be specified on net data types. The syntax is the same as primitive delays.
size is a range from
[msb:lsb](most-significant-bit to least-significant-bit).
- The msb and lsb must be integers, integer parameters or an expression that resolves to an integer constant.
- Either little-endian convention (the lsb is the smallest bit number) or big-endian convention (the lsb is the largest bit number) may be used.
- The maximum vector size is at least 65,536 bits (216).
array_size is from
[first_address:last_address].first_address and last_address must be integers, integer parameters, or an expression that resolves to integer.
- Either ascending or descending address order may be used.
- The maximum array size is at least 16,777,216 words (224).
strength (optional) is specified as
(strength1,strength0)or(strength0,strength1). See Logic Strengths for keywords.decay_time (optional) specifies the amount of time a trireg net will store a charge after all drivers turn-off, before decaying to logic X. The syntax is
(rise_delay,fall_delay,decay_time). The default decay is infinite.
Register Data Types
Keyword
Functionality
regunsigned variable of any bit size
integersigned 32-bit variable
timeunsigned 64-bit variable
realorrealtimedouble-precision floating point variable Register data types are used as variables in procedural blocks.
- Registers store logic values only (no logic strength).
- A register data type must be used when the signal is on the left-hand side of a procedural assignment.
New Data Types
Keyword
Functionality
wireortriSimple interconnecting wire worortriorWired outputs OR together wandortriandWired outputs AND together tri0Pulls down when tri-stated tri1Pulls up when tri-stated supply0Constant logic 0 (supply strength) supply1Constant logic 1 (supply strength) triregStores last value when tri-stated (capacitance strength) Net data types connect structural components together.
- Nets transfer both logic values and logic strengths.
- A net data type must be used when:
- A signal is driven by the output of some device.
- A signal is also declared as an input port or inout port.
- A signal is on the left-hand side of a continuous assignment.
Other Data Types
Other Types
Functionality
parameterRun-time constant for storing integers, real numbers, time, delays, or ASCII strings. Parameters may be redefined for each instance of a module.
specparamSpecify block constant for storing integers, real numbers, time, delays or ASCII strings
eventA momentary flag with no logic value or data storage. Often used for synchronizing concurrent activities within a module.
Data Type Declaration Examples
Data Type Examples
Notes
wire a, b, c;3 scalar nets tri1 [7:0] data_bus;8-bit net, pulls-up when tri-stated reg [1:8] result;an 8-bit unsigned variable reg [7:0] RAM [0:1023];a memory array; 8-bits wide, with 1K of addresses wire #(2.4,1.8) carry;a net with rise, fall delays wire (strong1,pull0) sum = a+b;net with drive strength and a continuous assignment trireg (small) #(0,0,35) ram_bit;net with small capacitance and 35 time unit decay time