FLIP-FLOPS

 6.1 Introduction

Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics circuits have no memory. In many applications, information regarding input values at a certain instant of time is required at some future time. Although every digital system is likely to have combinational circuits, most systems encountered in practice also include memory elements, which require that the system be described in terms of sequential logic. Circuits whose outputs depends not only on the present input value but also the past input value are known as sequential logic circuits. The mathematical model of a sequential circuit is usually referred to as a sequential machine.

A general block diagram of a sequential circuit is shown below in Figure 1.

           

   

Figure 1. Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a feedback path. The memory elements are devices capable of storing binary information within them. The combinational part of the circuit receives two sets of input signals: one is primary (coming from the circuit environment) and secondary (coming from memory elements). The particular combination of secondary input variables at a given time is called the present state of the circuit. The secondary input variables are also know as the state variables.

The block diagram shows that the external outputs in a sequential circuit are a function not only of external inputs but also of the present state of the memory elements. The next state of the memory elements is also a function of external inputs and the present state. Thus a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.

 Synchronous and Asynchronous Operation

Sequential circuits are divided into two main types: synchronous and asynchronous. Their classification depends on the timing of their signals.

Synchronous sequential circuits change their states and output values at discrete instants of time, which are specified by the rising and falling edge of a free-running clock signal. The clock signal is generally some form of square wave as shown in Figure 2 below.

Figure 2. Clock Signal

From the diagram you can see that the clock period is the time between successive transitions in the same direction, that is, between two rising or two falling edges. State transitions in synchronous sequential circuits are made to take place at times when the clock is making a transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). Between successive clock pulses there is no change in the information stored in memory.

The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined as the time during which the value of the clock signal is equal to 1. The ratio of the clock width and clock period is referred to as the duty cycle. A clock signal is said to be active high if the state changes occur at the clock's rising edge or during the clock width. Otherwise, the clock is said to be active low. Synchronous sequential circuits are also known as clocked sequential circuits.

The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits are binary cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the bit stored in it. Binary information can enter a flip-flop in a variety of ways, a fact which give rise to the different types of flip-flops. For information on the different types of basic flip-flop circuits and their logical properties, see the previous tutorial on flip-flops.

In asynchronous sequential circuits, the transition from one state to another is initiated by the change in the primary inputs; there is no external synchronization. The memory commonly used in asynchronous sequential circuits are time-delayed devices, usually implemented by feedback among logic gates. Thus, asynchronous sequential circuits may be regarded as combinational circuits with feedback. Because of the feedback among logic gates, asynchronous sequential circuits may, at times, become unstable due to transient conditions. The instability problem imposes many difficulties on the designer. Hence, they are not as commonly used as synchronous systems.

Summary of the Types of Flip-flop Behavior

Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types before proceeding further.

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip-flops are defined in Table 1.

 

       Table 1. Flip-flop Types

FLIP-FLOP NAME

FLIP-FLOP SYMBOL

CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION

EXCITATION TABLE

SR

S

R

Q(next)

0

0

Q

0

1

0

1

0

1

1

1

?

 

Q(next) = S + R'Q

SR = 0

Q

Q(next)

S

R

0

0

0

X

0

1

1

0

1

0

0

1

1

1

X

0

 

JK

J

K

Q(next)

0

0

Q

0

1

0

1

0

1

1

1

Q'

 

Q(next) = JQ' + K'Q

Q

Q(next)

J

K

0

0

0

X

0

1

1

X

1

0

X

1

1

1

X

0

 

D

D

Q(next)

0

0

1

1

 

Q(next) = D

Q

Q(next)

D

0

0

0

0

1

1

1

0

0

1

1

1

 

T

T

Q(next)

0

Q

1

Q'

 

Q(next) = TQ' + T'Q

Q

Q(next)

T

0

0

0

0

1

1

1

0

1

1

1

0

 

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its characteristic equation or excitation table. All flip-flops have output signals Q and Q'.

The characteristic table in the third column of Table 1 defines the state of each flip-flop as a function of its inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is equal to the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next state when S and R are both equal to 1 designates an indeterminate next state.

The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S and R respectively, except for the indeterminate case. When both J and K are equal to 1, the next state is equal to the complement of the present state, that is, Q(next) = Q'.

The next state of the D flip-flop is completely dependent on the input D and independent of the present state.

The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.

The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop inputs are known and we want to find the value of the flip-flop output Q after the rising edge of the clock signal. As with any other truth table, we can use the map method to derive the characteristic equation for each flip-flop, which are shown in the third column of Table 1.

During the design process we usually know the transition from present state to the next state and wish to find the flip-flop input conditions that will cause the required transition. For this reason we will need a table that lists the required inputs for a given change of state. Such a list is called the excitation table, which is shown in the fourth column of Table 1. There are four possible transitions from present state to the next state. The required input conditions are derived from the information available in the characteristic table. The symbol X in the table represents a "don't care" condition, that is, it does not matter whether the input is 1 or 0.

 Edge-Triggered Flip-flops

An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input.  The three basic types are introduced here: S-R, J-K and D.

Click on one the following types of flip-flop.  Then
its logic symbol will be shown on the left.  Notice the
small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.

Positive edge-triggered (without bubble at Clock input):
S-R, J-K, and D.

Negative edge-triggered (with bubble at Clock input):
S-R, J-K, and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock.  For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with the truth table for this type of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.

 

                    

As S = 1, R = 0.  Flip-flop SETS on the rising clock edge

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop.  The only difference is that this flip-flop has NO invalid state.  The outputs toggle (change to the opposite state) when both J and K inputs are HIGH.  The truth table is shown below.

Edge-triggered D flip-flop

The operations of a D flip-flop is much more simpler.  It has only one input addition to the clock.  It is very useful when a single data bit (0 or 1) is to be stored.  If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1.  If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0.  The truth table below summarize the operations of the positive edge-triggered D flip-flop.  As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.




 Pulse-Triggered (Master-Slave) Flip-flops

The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse, but the output does not reflect the input state until the falling edge of the clock pulse.  As this kind of flip-flops are sensitive to any change of the input levels during the clock pulse is still HIGH, the inputs must be set up prior to the clock pulse's rising edge and must not be changed before the falling edge.  Otherwise, ambiguous results will happen.  

The three basic types of pulse-triggered flip-flops are S-R, J-K and D.  Their logic symbols are shown below.  Notice that they do not have the dynamic input indicator at the clock input but have postponed output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered flip-flops, except for the way they are clocked.  These flip-flops are also called Master-Slave flip-flops simply because their internal construction are divided into two sections.  The slave section is basically the same as the master section except that it is clocked on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external inputs.  The logic diagram for a basic master-slave S-R flip-flop is shown below.

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